Tom Clarke
July 2008
Department of Electrical & Electronic Engineering
Imperial College London
This tutorial details how to use EAGLE with "non-standard" PCB processes - i.e. ones without plated through holes, or using only single-sided PCB. The Tutorial assumes that you have already read and followed the EAGLE Quick-Start Guide, and so are familiar with EAGLE operation. See Section 5 below for details of what PCBs can be manufactured quickly in the EEE department.
In order to use EAGLE successfully you may need to adjust track & pad sizes (Section 3) and autorouter (Section 4 ). Finally you should be aware of EAGLE board size limitations which depend on license.
EAGLE is configured through two sets of rules. Design Rule Check (DRC) rules determine minimum sizes and separations of objects. Rules can be modified using menus or loaded/saved from .dru files. Autorouter Setup determines which sides of the board are used for routing and how the routing process is optimised. the can be modified using menus or load/saved from .ctl files.
The combination of a .DRU file & a .CTL file does most (but not all) of the configuration necessary to make a board layout for a specific PCB process.
Both CTL & DRU file information is stored with boards, and can be saved to a new file if necessary. All boards are created with the default files.
This guide will focus on how to use EAGLE with low-quality processes where there are no plated through holes (PTH) & one side is preferred to two sides. Good quality layouts can still be made under these circumstances, however care is needed to use copper pouring effectively (both for routing and to provide electrical screening). There are a number of inter-dependent options the designer can use. We will examine these below.
The DRC rules (access dialog via Edit->DRC) can be changed to alter track and pad sizes. The library components come with small minimum sizes but these can be increased as necessary through DRC rules. Many PCB manufacturers will have their own EAGLE DRC rules which can be downloaded from a web-site. Otherwise they will publich information which can be entered by hand. The EAGLE default rules are conservative and normally therefore a design that checks with them will also check with most manufacturer rules.
Custom DRC rules may be necessary because the PCB etching process is low quality, or because lack of a solder mask makes tracks routed closely to pads liable to solder bridges. The precise dimensions can be changed individually - see the EAGLE manual for details. However one easy solution is to have one minimum dimension for everything, and use it to set dimensions in:
The DRC files ee_rules_20mil.dru and ee_rules_15mil.dru give examples of this with 20mil and 15mil (1mil = 1 thou = 1/1000" = 0.0254mm) dimensions. It is easy to modify these as required - e.g. if track width can be smaller than clearance dimensions. Note that small changes in these values can make big changes to layout, for example whether tracks can go between pads on an IC - this also depends on the drill size of the IC pin holes which comes from the component library chosen.
EAGLE by default treats all nets the same (default net class 0). It is possible to change the net class of nets (edit->change->net) to number 1-7. Each number corresponds to a different class which can be assigned its own minimum track width and drill sizes (edit->net class). It is very important to understand that the global DRC parameters and the net class parameters each specify minimum values - the actual track width will be determined by whichever parameter is largest for a given net class. Net class information is part of the board layout and not stored in an separate configuration file.
Typical use of net classes would be to ensure supplies has wider track-width than signals.
The combination of DRC rules and net classes determines track width, clearance, etc and is used to parametrise the auto-routing process.
No auto-router will solve every problem in layout but I like to do as much as possible without manual intervention. That way changes to the circuit can be made and auto-routed without too much time-consuming manual fine-tuning. Simple circuits will often auto-route perfectly with no post-routing cleanup.
Most Important.
The Routing Grid parameter (under Tools->Auto->General) determines how coarsely tracks are routed. It defaults to 50mil which allows a track to be routed between 0.1" (100mil) IC pins. The most common cause of auto-route failure is wrong choice of this parameter. It will need to be reduced for more dense designs, or if components are placed off 0.05" grid, or if Surface Mount (SMT) packages are used which have metric pad pitch. Obviously a value must be chosen which divides the pad pitch, or which is small enough that it can connect properly with each pad even though pads do not fall precisely onto the grid. However if too small a value is chosen routing may take too long. I like: 25mil, 20mil, 12.5mil, 19.685mil (0.5mm). For very dense digital designs with two tracks between IC pins a value must be chosen which allows this - experiment to see what is possible with different values.
| Board | Tab under Edit->Auto | Parameter | New Value | Notes |
| default auto-route Two-sided, with PTH |
Standard settings good for most production PCBs | |||
| Two-sided, no PTH | ||||
| As for default - see section below for how to get round lack of PTH | ||||
| Single-sided no PTH
|
General | Bottom layer direction | * | No preference in track direction |
| General | Top layer direction | n/a | No routing allowed | |
| Single-sided no PTH with wire links | General | Bottom layer direction | * | No preference in direction. Try also "|" and "-" values, since giving a preference to track direction will sometimes make better layouts. |
| General | Top layer direction | * | The top layer tracks here will need to be replaced by wire links -
you will need to add extra holes to do this - see the jumper library. No preference in direction. For difficult circuits needing a lot of wire links try giving top layer a direction 90 degrees away from bottom direction |
|
| Busses, Route, Optimise1, Optimise2, Optimise3 | Top layer cost | 99 | Forces route on bottom layer if possible, but allows top layer
routes where necessary. After PCB production top layer is replaced by
wire links. All tabs need to be changed. |
|
| As above with possibly better layout for copper pouring (fill). | Route, Optimise1 | Hugging | 0 | Adjusting these two hugging parameters downwards make tracks more
likely to be spread out. Generally this makes dense routing more
difficult, but it also makes layout more likely to auto-fill with all
filled areas connected. Useful for low density single-sided layouts. Generally where this does not work tracks may be adjusted manually after routing to allow better pouring: the Ratsnest command will delete polygon copper without changing tracks, so then auto-route will redo the copper pour. |
Table 1 - auto-route configuration
The EAGLE auto-router optimisation does not seem to understand single-sided boards with a single copper pour representing ground, because it will not always optimise to join up the different filled islands, even when moving one track sideways is all that is required. Setting the "hugging" parameters to 0 can help make the initial layout pour better, even so sometimes optimisation may have to be done by hand to avoid links connecting filled areas. Note that this solution will not work for all layouts, since non-zero initial hugging parameters help to allow routing of multiple tracks (particularly on digital layouts). You should always leave space at the edge of the board for filled area so that connections can extend easily all round the PCB.
Getting good quality auto-route will in general require careful adjustment of a number of parameters - see also the excellent EAGLE manual for further information.
See here for a worked example of how to lay out boards with SMT components for in-house production
The department can manufacture PCBs as in Table 2 (see manufacture page for availability). Note that in-house PCBs do not have silk screen (top-side painted legend). Where text is important it can be put on layer 1 (top-side copper). However this requires care. Text will interfere with tracks if it is too close, also it will make holes in poured copper. After placing layer 1 text use "ratsnest" to recalculate poured copper and show what the text will look like, and whether the holes generated break connectivity. Use DRC to check whether the text will interfere with existing tracks. Limit text to that absolutely necessary - typically testpoints, off-board connections, LEDs, and switches should be labelled.
| Number of copper layers | Silk screen | Solder mask | Plated-through holes | Time (exact time depends on workload, the figures below assume low loading, always check with technicians) | DRU file | CTL file | Notes |
| Single | no | yes | no | very quick (8 hours) | ee_rules_15mil.dru | route-top99.ctl | large pads, track, clearance, vias |
| Double | no | yes | no | quick (1 day) | ee_rules_15mil.dru | default.ctl | large pads, track, clearance, vias |
| Double | no | yes | yes | slow (2 days) | ee_rules_15mil_small_vias.dru | default.ctl | large pads, track, clearance |
Table 2 - in-house PCB capability
Fast PCBs in-house need to omit plated-through holes. However routing will assume that top & bottom tracks to a pin will always connect. This is correct when the top-side of the pin is visible and can be soldered (resistors, axial lead capacitors, ICs, transistors, circuit pins) but not when it is covered (trimmer resistors, most plugs and sockets). Radial lead capacitors can be soldered top-side if they are inserted with 1cm or so of lead between capacitor and board.
When making no PTH boards components which cannot be top-side soldered must have a tRestrict (41) layer Rectangle placed over pins (Draw->Rectangle - then set layer 41). This will prevent the auto-router from routing top-side copper onto these pins. You can choose how much you do this (e.g. whether you restrict radial-lead capacitors).
See zcontr-noPTH.brd in the examples directory for how to use tRestrict layer in this way.
Note that Vias will still be generated by auto-route where necessary and must be connected by hand (using special pins or short lengths of wire soldered top & bottom). however standard auto-route settings minimise number of Vias.
DRC files for in-house production depend on two things, board manufacture, and soldering. See the lab technicians for the sizes which can be reproduced without errors, generally widths and spacings of 15 mil (15/1000") should be OK, check if you use less. However, to make boards more robust and easier to hand solder it is helpful to increase track widths and clearances as much as possible. Particularly important for soldering is pad width, and clearance pad to anything else. Often these parameters must be adjusted by hand - too large and the board will not easily autoroute.
Put some text, e.g. if nothing else "Top" or "Bottom" on top or bottom copper layers (1,16) to make sure these get manufactured the right way round (not mirrored). Providing one layer is identified the other will match it and needs no further identification.
From BRD window, do
File->CAM Processor
(CAM window) File->Open->Job
select excellon.cam, then click "process job" - will generate .DRD & .DRI files in same directory as .BRD for automatic drilling
(CAM window) File->Open->Job
select gerb274x.cam, then select "process job" - will generate CMP, SOL, GPI, PLC, STC,STS files in same directory as .BRD.
Collect the above 8 files in a ZIP file (check extensions carefully) and send this to the lab technicians for in-house processing. See EE2 lab pages for further details of how to contact technicians and submit boards.
See Examples directory for a number of EAGLE example boards and schematics - the board name indicates the technology.